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High performance data acquisition communication line
Hadámek, Jakub ; Petyovský, Petr (referee) ; Valach, Soběslav (advisor)
The aim of this thesis is the acquisition of data from the AD converter and it’s transfer via the JESD204B interface to FPGA with the following transformation and transfer to PC through 100G Ethernet or PCI Express interface. The first part of the thesis is focused on the introduction to used technologies and hardware and analysis of the solution of this project. Second part of the thesis describes solution and it’s functionality. I created HDL design which allows to transfer data from AD converter using both of the interfaces mentioned above. I also created software application for OS Linux which allows to receive and store incoming data in PC. In the end, the results of the measurement using the converter board are presented and discussed.
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High speed acquisition system
Svoboda, Tomáš ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.
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High performance data acquisition communication line
Hadámek, Jakub ; Petyovský, Petr (referee) ; Valach, Soběslav (advisor)
The aim of this thesis is the acquisition of data from the AD converter and it’s transfer via the JESD204B interface to FPGA with the following transformation and transfer to PC through 100G Ethernet or PCI Express interface. The first part of the thesis is focused on the introduction to used technologies and hardware and analysis of the solution of this project. Second part of the thesis describes solution and it’s functionality. I created HDL design which allows to transfer data from AD converter using both of the interfaces mentioned above. I also created software application for OS Linux which allows to receive and store incoming data in PC. In the end, the results of the measurement using the converter board are presented and discussed.
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|
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High speed acquisition system
Svoboda, Tomáš ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.
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